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CY62128DV30
1-Mb (128K x 8) Static RAM
Features
* Very high speed: 55 and 70 ns * Wide voltage range: 2.2V to 3.6V * Pin compatible with CY62128V * Ultra-low active power -- Typical active current: 0.85 mA @ f = 1 MHz -- Typical active current: 5 mA @ f = fMAX * Ultra-low standby power * Easy memory expansion with CE1, CE2, and OE features * Automatic power-down when deselected * Available in Pb-free and non Pb-free 32-lead SOIC, 32-lead TSOP and 32-lead Small TSOP, non Pb-free 32-lead Reverse TSOP packages also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW. The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (OE HIGH), or during a write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable (WE) LOW). Writing to the device is accomplished by taking Chip Enable 1 (CE1) LOW with Chip Enable 2 (CE2) HIGH and Write Enable (WE) LOW. Data on the eight I/O pins is then written into the location specified on the Address pin (A0 through A16). Reading from the device is accomplished by taking Chip Enable 1 (CE1) LOW with Chip Enable 2 (CE2) HIGH and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/Oo through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH) or during a write operation (CE1 LOW, CE2 HIGH), and WE LOW).
Functional Description[1]
The CY62128DV30 is a high-performance CMOS static RAM organized as 128K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device
Logic Block Diagram
Data in Drivers
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 ROW DECODER
I/O0 I/O1
SENSE AMPS
I/O2 I/O3 I/O4 I/O5
128K x 8 ARRAY
CE1 CE2 WE
COLUMN DECODER
Powerdown
I/O6 I/O7
A 12 A 13 A 14
OE
Note: 1. For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05231 Rev. *H
*
198 Champion Court
A 15 A 16
*
San Jose, CA 95134-1709 * 408-943-2600 Revised June 19, 2006
CY62128DV30
Pin Configurations[2]
Top View
SOIC
DNU A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3
A11 A9 A8 A13 WE CE2 A15 VCC DNU A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TSOP I Top View (not to scale)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
A11 A9 A8 A13 WE CE2 A15 VCC DNU A16 A14 A12 A7 A6 A5 A4
25 26 27 26 28 29 30 31 32 1 2 3 4 5 6 7 8
STSOP Top View (not to scale)
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3
A4 A5 A6 A7 A12 A14 A16 DNU VCC A15 CE2 WE A13 A8 A9 A11
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Reverse TSOP I Top View (not to scale)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
A3 A2 A1 A0 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE1 A10 OE
Product Portfolio
Power Dissipation Operating, ICC (mA) VCC Range (V) Product CY62128DV30L CY62128DV30LL Min. 2.2 Typ. 3.0 Max. 3.6 Speed (ns) 55/70 55/70 f = 1 MHz Typ.[4] 0.85 0.85 Max. 1.5 1.5 5 5 f = fMAX Typ.[4] Max. 10 10 Standby, ISB2 (A) Typ.[4] 1.5 1.5 Max. 5 4
Notes: 2. NC pins are not connected to the die. 3. DNU pins have to be left floating or tied to Vss to ensure proper application. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C.
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CY62128DV30
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential .......................................................... -0.3V to 3.9V DC Voltage Applied to Outputs in High-Z State[5] ....................................-0.3V to VCC + 0.3V DC Input Voltage[5] ................................ -0.3V to VCC + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA
Operating Range
Range Industrial Ambient Temperature (TA) -40C to +85C VCC[6] 2.2V to 3.6V
DC Electrical Characteristics (Over the Operating Range)
CY62128DV30-55/70 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current - CMOS Inputs Test Conditions 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 2.2 < VCC < 2.7 2.7 < VCC < 3.6 GND < VI < VCC GND < VO < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = 3.6V, IOUT = 0mA, CMOS level IOH = -0.1 mA IOH = -1.0 mA IOL = 0.1 mA IOL = 2.1 mA 1.8 2.2 -0.3 -0.3 -1 -1 5 0.85 1.5 1.5 1.5 1.5 Min. 2.0 2.4 0.4 0.4 VCC + 0.3 VCC + 0.3 0.6 0.8 +1 +1 10 1.5 5 4 5 4 A A A A mA V V V Typ.[4] Max. Unit V
ISB1
CE1 > VCC - 0.2V, CE2 < 0.2V, L VIN > VCC - 0.2V, VIN < 0.2V, LL f = fMAX (Address and Data Only), f = 0 (OE, WE,) CE1 > VCC - 0.2V, CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC=3.6V L LL
ISB2
Automatic CE Power-down Current - CMOS Inputs
Capacitance[7]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz VCC = VCC(typ) Max. 8 8 Unit pF pF
Thermal Resistance[7]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Test Conditions SOIC TSOP I RTSOP STSOP 69 34 93 17 93 17 65 15 Unit C/W C/W Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit Thermal Resistance (Junction to Case) board
Notes: 5. VIL(min.) = -2.0V for pulse durations less than 20 ns. VIH(max.) = VCC+0.75V for pulse durations less than 20 ns. 6. Full device operation requires linear ramp of VCC from 0V to VCC(min) and VCC must be stable at VCC(min) for 500 s. 7. Tested initially and after any design or process changes that may affect these parameters.
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CY62128DV30
AC Test Loads and Waveforms[8]
R1 VCC OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 VCC 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V 2.5V (2.2V - 2.7V) 16600 15400 8000 1.20 3.0V (2.7V - 3.6V) 1103 1554 645 1.75 Unit V
Parameters R1 R2 RTH VTH
Data Retention Characteristics
Parameter VDR ICCDR tCDR[4] tR[8] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = 1.5V, CE1 > VCC - 0.2V, CE2 < 0.2V, L VIN > VCC - 0.2V or VIN < 0.2V LL 0 100 Conditions Min. 1.5 4 3 ns s Typ.[4] Max. Unit V A
Data Retention Waveform
DATA RETENTION MODE VCC CE1 V CC(min.) tCDR VDR > 1.5V VCC(min.) tR
or
CE 2
Note: 8. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s.
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CY62128DV30
Switching Characteristics (Over the Operating Range)[9]
CY62128DV30-55 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE
[12]
CY62128DV30-70 Min. 70 Max. Unit ns 70 10 70 35 5 25 10 25 0 70 70 60 60 0 0 50 30 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 10 ns ns
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW or CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z
[10]
Min. 55
Max.
55 10 55 25 5 20 10 20 0 55 55 40 40 0 0 40 25 0 20 10 Z[10, 11]
OE HIGH to High Z[10, 11] CE1 LOW or CE2 HIGH to Low Z[10] CE1 HIGH or CE2 LOW to High CE1 LOW or CE2 HIGH to Power-up CE1 HIGH or CE2 LOW to Power-down Write Cycle Time CE1 LOW or CE2 HIGH to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High WE HIGH to Low Z[10, 11] Z[10]
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[13, 14]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Notes: 9. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than t. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals. 13. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 14. WE is HIGH for Read cycle.
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CY62128DV30
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[11, 14, 15]
ADDRESS tRC CE1 CE2 tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% ISB tHZOE tHZCE HIGH IMPEDANCE
ICC
Write Cycle No. 1 (WE Controlled)[12, 16, 17, 18]
ADDRESS tSCE CE1
CE2 tSCE tAW tSA WE tPWE tHA
tSD DATA I/O NOTE 18 DATAIN VALID
tHD
Notes: 15. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 16. Data I/O is high-impedance if OE = VIH. 17. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
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CY62128DV30
Switching Waveforms (continued)
Write Cycle No. 2 (CE1 or CE2 Controlled)[12, 16, 17, 18]
tWC ADDRESS tSCE CE1 tSA CE2 tSCE tAW tPWE WE t SD DATA I/O DATA VALID tHD tHA
Write Cycle No. 3 (WE Controlled, OE LOW)[10, 16, 17]
t WC ADDRESS t SCE CE 1
CE 2 t SCE t AW t SA WE t PWE t HA
tSD DATA I/O
t HD
DON'T CARE
t HZWE
DATA VALID t LZWE
Truth Table
CE1 H X L L L CE2 X L H H H WE X X H H L OE X X L H X I/O0-I/O7 High Z High Z Data out High Z Data In MOde Deselet/Power-down Deselet/Power-down Read Output Disabled Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
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CY62128DV30
Ordering Information
Speed (ns) 55 Ordering Code CY62128DV30L-55SI CY62128DV30LL-55SI CY62128DV30LL-55SXI CY62128DV30L-55ZI CY62128DV30LL-55ZI CY62128DV30LL-55ZXI CY62128DV30L-55ZAI CY62128DV30LL-55ZAI CY62128DV30LL-55ZAXI CY62128DV30L-55ZRI CY62128DV30LL-55ZRI CY62128DV30LL-55ZRXI 70 CY62128DV30L-70SI CY62128DV30LL-70SI CY62128DV30LL-70SXI CY62128DV30L-70ZI CY62128DV30LL-70ZI CY62128DV30LL-70ZXI CY62128DV30L-70ZAI CY62128DV30LL-70ZAI CY62128DV30LL-70ZAXI CY62128DV30L-70ZRI CY62128DV30LL-70ZRI Package Diagram 51-85081 32-lead SOIC 51-85081 32-lead SOIC 51-85081 32-lead SOIC (Pb-Free) 51-85056 32-lead TSOP Type 1 51-85056 32-lead TSOP Type 1 51-85056 32-lead TSOP Type 1 (Pb-Free) 51-85094 32-lead Small TSOP 51-85094 32-lead Small TSOP 51-85094 32-lead Small TSOP (Pb-Free) 51-85089 32-lead Reverse TSOP 51-85089 32-lead Reverse TSOP 51-85089 32-lead Reverse TSOP 51-85081 32-lead SOIC 51-85081 32-lead SOIC 51-85081 32-lead SOIC (Pb-Free) 51-85056 32-lead TSOP Type 1 51-85056 32-lead TSOP Type 1 51-85056 32-lead TSOP Type 1 (Pb-Free) 51-85094 32-lead Small TSOP 51-85094 32-lead Small TSOP 51-85094 32-lead Small TSOP (Pb-Free) 51-85089 32-lead Reverse TSOP 51-85089 32-lead Reverse TSOP Package Type Operating Range Industrial
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CY62128DV30
Package Diagrams
32 LD (450 Mil) SOIC32-Lead (450-Mil) SOIC (51-85081)
16 1
0.546[13.868] 0.566[14.376]
0.440[11.176] 0.450[11.430]
DIMENSIONS IN INCHES[MM] PACKAGE WEIGHT 1.42gms
PART # S32.45 STANDARD PKG. SZ32.45 LEAD FREE PKG.
MIN. MAX.
17
32
0.793[20.142] 0.817[20.751]
0.006[0.152] 0.012[0.304]
0.101[2.565] 0.111[2.819]
0.118[2.997] MAX. 0.004[0.102] 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990]
0.050[1.270] BSC.
0.004[0.102] MIN. 0.014[0.355] 0.020[0.508] SEATING PLANE
51-85081-*B
32-Lead TSOP Type I (8 x 20 mm) (51-85056)
51-85056-*D
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CY62128DV30
Package Diagrams (continued)
32-Lead STSOP (8 x 13.4 mm) (51-85094)
51-85094-*D
32-Lead RTSOP (51-85089)
51-85089-*C
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05231 Rev. *H
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62128DV30
Document History Page
Document Title: CY62128DV30 1-Mb (128K x 8) Static RAM Document Number: 38-05231 REV. ** *A ECN NO. Issue Date 117691 127314 08/27/02 5/27/03 Orig. of Change JUI MPR New Data Sheet Changed from Advance Information to Preliminary Changed Isb2 to 5 A (L), 4 A (LL) Changed Iccdr to 4 A (L), 3 A (LL) Changed Cin from 6 pF to 8 pF Changed from Preliminary to Final Add 70-ns speed, updated ordering information Changed Icc 1 MHz typ from 0.5 mA to 0.85 mA Added Lead-Free Packages in Ordering Information Table Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Corrected CE1 and CE2 waveforms on Write Cycle No.1 on Page# 6. Edited the Write Cycle No.1 switching waveform Data I/O to include Don't Care Condition on Page# 6 Updated the ordering information on Page # 8 Added Thermal Resistance numbers for RTSOP package Updated Ordering Information table by replacing Package Name column with Package Diagram Updated the Block Diagram on page # 1 Changed pin# 1 of SOIC and STSOP I, pin # 9 of TSOP I and RTSOP I from NC to DNU and added footnote# 3 Description of Change
*B *C *D *E
128342 129002 347394 395936
07/23/03 08/29/03 See ECN See ECN
JUI CDY PCI SYT
*F
428906
See ECN
AJU
*G *H
464721 470383
See ECN See ECN
NXR NXR
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